1. Field of the Invention
The present invention relates to a process for producing a semiconductor device and, more particularly, to a process for producing a MOS type memory cell having a so-called LDD structure by forming a diffusion region on a silicon substrate using, as a mask, a gate electrode having a side wall.
2. Description of the Related Art
FIGS. 6(a) to 6(f) show a typical conventional process for producing a MOS type memory cell. In this process, a polysilicon layer 43 as a gate material is formed on a Si substrate 41 through the intermediary of a gate oxide film 42. As NSG layer (non-doped silicate glass layer) 44 is formed as required on the polysilicon layer 43 for the purpose of improving the gate characteristic, as shown in FIG. 6. Then, a resist layer 45 is formed thereon. Subsequently, a wet etching is effected on a resist layer 45 so as to form this resist layer into a predetermined pattern for forming gate electrode. Subsequently, a photo-etching is conducted to form a laminate structure composed of a gate electrode 49 having the polysilicon layer 43 and the NSG layer 44 and the resist layer 45, as shown in FIG. 6(a).
Then, after the removal of the resist layer 45, an SiO.sub.2 layer 46a having a gate electrode 49 is formed on the Si substrate 41, as shown in FIG. 6(b), followed by an RIE (reactive ion etching) method for forming a side wall 46, as shown in FIG. 6(c).
In a subsequently step, As+ ions 47 are injected as shown in FIG. 6(d) while the gate electrode 49 and the side wall 46 are used as a mask, whereby an ion injected layer (not shown) is formed. Then, a heat-treatment is conducted to form a source-drain diffusion region 48 on the Si substrate 41 as shown in FIG. 6(e).
Then, a BPSG (boron-doped phospho-silicate glass) film 60 as an inter-layer insulating film is laminated on the entire area. Contact holes 50 are formed through the BPSG film so as to reach the diffusion region 48 and a metallic wiring 51 is laid to fill the contact holes 50, whereby a MOS type memory cell is formed as shown in FIG. 6(f).
This known process suffers from the following disadvantages. Namely, there is a risk that crystalline defects tend to be generated in the side wall edge portion 46b and in the diffusion region 48, as a result of injection of As+ ions 47 (see FIG. 6(d)) and/or the heat treatment (see FIG. 6(e)).
More specifically, the RIE method conducted for the purpose of forming the side wall 46 (see FIG. 6(c)) also damages the Si substrate. In the subsequent heat treatment, defects are produced around the damaged portions of the Si substrate since these damaged portions serve as nuclei. In addition, the side wall edge portion 46b forms a steep slope with respect to the surface of the Si substrate so that a large stress i incurred on the surface region of the Si substrate. As a consequence, the stress is transferred into the Si substrate through a subsequent heat treatment, with the result that crystalline defect is formed in the Si substrate.
In addition, there is a risk that the BPSG layer 60 is diffused as impurities into the diffusion region 48 during formation of this film 60. This undesirably increases electrical leak in the products add reduces the yield of the products.
The following process has been proposed to overcome the above-described problems. In this proposed process an SiO.sub.2 layer 63 is formed on a gate electrode 62 of a Si substrate 61 as shown in FIG. 7(a), followed by a combination of an RIE method and an HF etching method so that a side wall 51 is formed while leaving an SiO.sub.2 film on the gate electrode 62, as shown in FIG. 7(b). According to this method, damaging of the Si substrate 61 due to RIE method is avoided. In addition, a taper 51a is formed by the residue of the SiO.sub.2 film on the end of the side wall, thus relieving stress applied to the Si substrate. However, when ion injection is conducted on this laminate structure, oxygen is introduced into the Si substrate from the SiO.sub.2 film formed thereon, so that a crystalline defect is formed in the diffusion layer formed by the heat treatment. More specifically, referring to FIG. 8, the defect density is small when the thickness of a SiO.sub.2 film 64 ranges between 300 and 500 .ANG. but is increased when the thickness is reduced, in case where the As+ ions are injected at an energy density of 80 KeV and a dosage 5.times.10.sup.15 cm.sup.-2. In this process, however, the film thickness largely fluctuates because of use the RIE method for forming the side wall, so that it is not easy to control the film thickness to the above-mentioned restricted range. Thus, the SiO.sub.2 film thickness below 300 A undesirably allows implantation of a large quantity of oxygen atoms from the SiO.sub.2 film into the Si substrate, thus inducing generation of crystalline defects.
The current demand for larger scale of integration of semiconductor devices requires that the diffusion layer be formed to a smaller depth and with a high quality devoid of any defect. A process which employs a short heat treatment at high temperature subsequent to the ion injection of FIG. 6(d) is considered as being promising process for obtaining such a thin diffusion layer of a high quality. According to this process, however, slip lines are liable to be formed around transfer loops which are generated during the heat-treatment and which function as nuclei, due to a rapid cooling which is essential in the short heat-treatment. More specifically, as shown in FIG. 9, defects tend to be generated in two stages: namely, in the interface S1 between the amorphous Si and the crystalline Si of the Si substrate 1 and in a region near the projection range (Pr) S2. In FIG. 9, S1a and S2a show defects which originate from transfer loops. In particular, the defect S1a generated in the deep interface S1 is liable to cause a leak in the diffusion layer.
The following reference is available as showing an art relevant to the invention of this application:
M. Tamura et al, Japanese Journal of Applied Physics, 27(12), 2209-2217, 1988